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(R)
CA3224E
UCT PROD E NT OLETE REPLACEM Sheet OBS DataDED MEN ECOM
October 2002
FN1553.2
NO R
Automatic Picture Tube Bias Control Circuit Description
The CA3224E is an automatic picture tube bias control circuit used in color TV receiver CRT drive circuits. It is used to provide dynamic bias control of the grey scale both initially and over the CRT operating life, compensating for CRT cutoff changes. The CA3224E provides automatic continuous control of the cutoff current in each gun of a three-gun color CRT. From an input pulse amplitude proportional to the difference between the desired and the actual CRT cutoff, a gated sample/hold circuit generates a DC correction voltage which correctly biases the CRT driver circuit. The sample/hold bias correction takes place each frame following the vertical blanking. Figure 1 shows a block diagram of the CA3224E. The functions include three identical servo loop transconductance amplifiers with a sample/hold switch and buffer amplifier plus control logic, internal bias and a mode.
Features
* Automatic Picture Tube Bias Cutoff Control * Automatic Background Color Balance * Eliminates Grey Scale Adjustments * Compensates for Cathode-to-Heater Leakage * Electrostatic Protection on All Pins * Servo Loop Design * Wide Dynamic Range * Three-Gun Control * Minimal External Components
Part Number Information
PART NUMBER CA3224E TEMP. RANGE (oC) -40 to 85 PACKAGE 22 Ld PDIP PKG. NO. E22.4
Pinout
CA3224E (PDIP) TOP VIEW
GROUND CHANNEL 1 INPUT CHANNEL 1 FREQ COMPENSATION CHANNEL 2 INPUT CHANNEL 2 FREQ COMPENSATION CHANNEL 3 INPUT CHANNEL 3 FREQ COMPENSATION VERTICAL INPUT GROUND HORIZONTAL INPUT GRID PULSE OUTPUT
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19 18 17 16 15 14 13 12
VCC CHANNEL 1 HOLD CAP CHANNEL 1 OUTPUT CHANNEL 2 HOLD CAP CHANNEL 2 OUTPUT CHANNEL 3 HOLD CAP CHANNEL 3 OUTPUT VREF BYPASS AUTO BIAS LEVEL ADJUST AUTO BIAS PULSE OUTPUT PROGRAM PULSE OUTPUT
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
CA3224E
Absolute Maximum Ratings TA = 25oC
Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 to VCC Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 10V 10%
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications At TA = 25oC, VCC = 10V, VBIAS = 3.75V, VV (Pin 8) = VH (Pin 10) = 6.0V, S1 = A, S2 = A,
See Test Circuit and Timing Diagrams PARAMETER Supply Current Reference Voltage Input Current Output Current Source Sink Output Buffer Input Current Voltage Gain Transconductance 17,19, 21 17,19, 21 TEST PIN NO. SYMBOL 22 2, 4, 6 2, 4, 6 17,19, 21 ICC VREF II lOM+ lOMII AV gM VOL VOH lOM11 VOL VOH 12 VOL VOH 8 10 13 VV VH Measure at t4 VIN = 7.2V, S1 = B VBIAS = 0.5V, Measure at t 6, S1 = B VBIAS = 7.0V, Measure at t 6, S1 = B VOUT = 6.5V, VIN At pins 16, 18, 20, Measure at t4 , S1 = B Measure at t6, VIN = 8mVP-P at 40kHz, S1 = B Measure at t1 Measure at t4 Measure at t4, S2 = B Measure at t4 Measure at t1 Measure at t6 Measure at t1 See Figure 3 See Figure 3 t0 to t2, Note 2 t0 to t7, Note 2 11 t0 to t3, Note 2 t0 to t5, Note 2 12 t0 to t5, Note 2 t0 to t7, Note 2 TEST CONDITIONS MIN 5.6 0.8 0.97 50 TYP 6.0 MAX 65 6.4 250 -0.8 150 1.07 100 UNITS mA V nA mA mA nA mS
Auto Bias Pulse
Output Low High Current Sink
13
6.05 2.5 4.2 8.2 835 1270 899 1080 1080 1270
6.0 6.0 -
0.3 0.4 0.4 842 1275 905 1084 1084 1275
V V mA V V V V V V s s s s s s
Grid Pulse Output
Low High
Program Pulse Output
Low High
Vertical Input Horizontal Input Auto Bias Pulse Timing Start Finish Grid Pulse Timing Start Finish Program Pulse Timing Start Finish NOTE:
2. All time measurements are made from 50% point to 50% point.
2
CA3224E Test Circuit
+10V 3.65K 1 VIN1 2 22 B 21 S1 3 0.047 F VIN2 4 19 S1 5 0.047 F VIN3 6 17 S1 CA3224E 7 VERTICAL INPUT 0.047 F 8 16 15 18 B A 20 B A A 0.12F VBIAS
output goes high. This is used to set the RGB drive of the companion chroma/luma circuit to black level. The auto-bias pulse stays high for 7 horizontal periods during the auto-bias cycle. On the 15th horizontal sync pulse, the internal logic initiates the setup interval. During the setup interval, the cathode current is increased to a reference value (A in Figure 5) through the action of the grid pulse. The cathode current causes a voltage drop across R S. This voltage drop, together with the program pulse output results in a reference voltage at VS (summing point) which causes capacitor C1 to charge to a voltage proportional to the reference cathode current. The setup interval lasts for 3 horizontal periods. On the 18th horizontal sync pulse the grid pulse output goes high, which through the grid pulse amplifier/inverter, causes the cathode current to decrease. The decrease in cathode current results in a positive recovered voltage pulse with respect to the setup reference level at the VS summing point. The positive recovered voltage pulse is summed with a negative voltage pulse caused by the program pulse output going low (cutting off Diode D1 and switching in resistors R1 and R2). Any difference between the positive and negative pulses is fed through capacitor C1 to the transconductance amplifier. The difference signal is amplified in the transconductance amplifier and charges the hold capacitor C2, which, through the buffer amplifier, adjusts the bias on the driver circuit. Components RS, R1, and R2 must be chosen such that the program pulse and the recovered pulse just cancel at the desired cathode cutoff level.
VOUT1 3.65K 0.12F
VOUT2 3.65K 0.12F
47F +
VOUT3
9
14
+20V 3.32K 1.50K 1.0K B +10V
HORIZONTAL INPUT
10 11
13 20K 12 S2
A 1.5K
Device Description and Operation (See Figures
1, 2, 4 and 5)
During the vertical retrace interval, 13 horizontal sync pulses are counted. On the 14th sync pulse the auto-bias pulse
CHAN FREQ 1 IN COMP 2 3 AMPLIFER NO. 1 1 HOLD CHAN CHAN FREQ CAPACITOR 1 OUT 2 IN COMP 21 20 4 5 AMPLIFER NO. 2 1 gM
HOLD CAPACITOR 19
CHAN 2 OUT 18
CHAN FREQ 3 IN COMP 6 7
HOLD CAPACITOR 17
CHAN 3 OUT 16
BUFFER AMP x1
BUFFER AMP x1
AMPLIFER NO. 3 1
BUFFER AMP x1
+ gM
2 3
+
2
+ gM
2 3
3
VREF
MODE SWITCH
BIAS
LOGIC
1 GND MODE SWITCH 1 2 3
9 GND STATE SET-UP SENSE OPEN
22 VCC
15 VREF BYPASS
8 VERT IN
10 HORIZ IN
11 GRID PULSE OUT
12 PROG PULSE OUT
13 AUTO BIAS PULSE OUT
14 AUTO BIAS LEVEL ADJUST
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
3
CA3224E
t0
t1
t2
t3
t4 t5
t6
t7
VERTICAL INPUT (PIN 8) HORIZONTAL INPUT (PIN 10) 1 AUTO BIAS PULSE OUTPUT (PIN 13) GRID PULSE OUTPUT (PIN 11) PROGRAM PULSE OUTPUT (PIN 12)
VERTICAL BLANKING
2
3
12
13 14 15
16 17
18
19
20 21
22
23
MODE SWITCH (SEE FIGURE 1)
OPEN
SET-UP
SENSE
OPEN
FIGURE 2. FUNCTIONAL TIMING DIAGRAMS
VERTICAL SIGNAL 0V
VV 0.5ms 16.683ms fV = 59.94Hz
HORIZONTAL SIGNAL 0V 12s
VH
fH = 15734.264Hz
63.55 s
FIGURE 3. VERTICAL AND HORIZONTAL INPUT SIGNALS
4
CA3224E
+230V 12K 2.2K R G B +12V Q1 CATH DRIVE 1 SG RIN 0.047 3 CC GIN 0.047 5 BIN 0.047 7 12 +10V TO BCH 22 9 AUTO-BIAS PULSE 13 10 8 11 15 14 20K AUTO BIAS LEVEL ADJUST HORIZONTAL INPUT VERTICAL INPUT 6 17 CA224E 16 4 18 19 2 20 ROUT 21 10K Q3
+
33F 3.9K
+10V 1.5K
+
10F
GRID PULSE AMPLIFIER INVERTER
R CHROMA/ LUMA 2.7K CIRCUIT G B
TO R DRIVER BIAS 5K
RFB 160K
RS 560 1% SUMMING POINT 200 VS 0.12 C1 R2 62K 1% TO RCH D1
+
C2
10F GOUT GIN
+
10F
Q2 BIAS
20K
+
BOUT 47F
TO B DRIVER -24V PROGRAM RGB TO BLACK LEVEL
9.1K 2.7K R1 39K 1%
NOTE: 3. One of three identical driver circuits shown. FIGURE 4. TYPICAL APPLICATION CIRCUIT
Electrostatic Protection (Note)
ICATHODE (mA)
A B 0 SET-UP SENSE VCATHODE GRID (V)
When correctly designed for ESD protection, SCRs can be highly effective, enabling circuits to be protected to well in excess of 4kV. The SCR ESD-EOS protection structures used on each terminal of the CA3224E are shown schematically in either Figures 6A or 6B. Although ESD-EOS protection is included in the CA3224E, proper circuit board layout and grounding techniques should be observed.
NOTE: For further information on CA3224E protection structures refer to: AN7304, "Using SCRs as Transient Protection Structures in Integrated Circuits", by L.R. Avery.
FIGURE 5. PICTURE TUBE V-I CURVE
TO ACTIVE CIRCUIT TO ACTIVE CIRCUIT
RSENSE
RHOLD
RHOLD
POSITIVE SUBSTRATE TRANSIENT NEG. TRANSIENT PROTECT (A) PROTECT
NEGATIVE POSITIVE TRANSIENT TRANSIENT PROTECT (B) PROTECT
FIGURE 6A. FIGURE 6. TRANSIENT PROTECTION
FIGURE 6B.
5
CA3224E Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2
E22.4 (JEDEC MS-010-AA ISSUE C)
22 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-
MILLIMETERS MIN 0.39 3.18 0.356 1.15 0.229 27.06 0.13 9.91 8.39 MAX 5.33 4.95 0.558 1.65 0.381 28.44 10.79 9.90 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.125 0.014 0.045 0.009 1.065 0.005 0.390 0.330
MAX 0.210 0.195 0.022 0.065 0.015 1.120 0.425 0.390
-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
A A1 A2 B B1 C D D1 E
-C-
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.400 BSC 0.115 22 0.500 0.160
2.54 BSC 10.16 BSC 2.93 22 12.70 4.06
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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